Design and compare the HA and FA circuits using Gate Diffusion Input (GDI) technique based on 18 nm FinFET technology for improved power efficiency and performance

The most significant challenge in designing adders using the gate diffusion input (GDI) technology is minimizing the anticipated area, power consumption, and propagation delay. In this article, we have compared both the Half Adder (HA) and Full Adder (FA) circuits using the GDI technique. After simulation, it was determined that the HA circuit performed better in terms of power, delay, power delay product (PDP), and energy-delay product (EDP), while the FA circuit consumed a larger area for its design. The PDP of the HA circuit at 1 V is $2.237\times 10^{-16}{\mathrm{J}}$, at 0.9 V it is $1. 549\times 10^{-16}J$, and at 0.8 V it is $1. 259\times 10^{-16} {\mathrm{J}}$, respectively. The EDP at 1 V is $50.057\times 10^{-22}$, at 0.9 V it is $23.995 \times 10^{-22}$, and at 0.8 V it is $15.850\times 10^{-22}$, respectively. These HA and FA circuits may find applications in both biological and medical healthcare applications.