An Optimal Submodule Capacitor Sizing Method for Modular Multilevel Converters for HVDC Applications

Select existing submodule capacitor sizing methods were presented and a new method that results in minimized submodule capacitor size was proposed. The proposed design method considers the fact that the fundamental submodule capacitor voltage component is the major contributor to the SM capacitor ripple voltage. It was found that the harmonics contribution to the submodule capacitor ripple voltage is insignificant. The use of circulating current suppression controllers that drive the harmonics in the arm current to practically zero further justified the design method. The design method was verified through simulation of an active modular multilevel converter in rectifier mode using PSIM software. It was found that the resulting capacitor size met the submodule capacitor voltage ripple design specification. A small submodule capacitor size reduces the cost and the physical footprint of a converter.