Performance Comparison of Charge Pump Circuits Against Dickson CPs for PLL Application

This paper investigates the performance of different charge pump (CP) circuits. Specifically, it examines the effectiveness of various Dickson charge pump circuits, including single clock CP, Taegun Yim et al CP, and CTS with DK-CP. Additionally, it evaluates different charge pump designs such as two-stack gate-controlled with bias circuit CP, Suraj Kumar et al CP, and transmission gate cascade current mirror CP. This study measures their performance based on phase noise, power consumption, lock time, and reference spur. The simulations for this study were conducted using Cadence Virtuoso software with CMOS 90nm technology. The supply voltage for both the basic CP and DK-CP designs was set to 1V. The results show that the basic CP design consumed 0.06mW of power, while the DK-CP design consumed 5.52uW. In terms of phase noise, the basic CP design exhibited -139.9dBC/Hz, whereas the DK-CP design had a phase noise of -105.18dBc/Hz.