Capacitance RF Characterization and Modeling of 28 FD-SOI CMOS Transistors down to Cryogenic Temperature

In this study we investigate the capacitance characterization and modeling of CMOS transistors integrated in 28nm Ultra Thin Body and Box (UTBB) Fully Depleted Silicon On Insulator (FD-SOI) technology from room temperature down to 4. 2K. 100MHz to 40 GHz RF transistor capacitances with different gate lengths are carefully extracted as a function of temperature and modeled. We highlight the impact of the carrier freeze-out in the substrate and, for the first time, the capacitance frequency behavior with the well resistance variation due to the cooling.