IEC ESD Co-Design Methodology for On-Chip Protection at High Voltage Fault Tolerant Transceivers

System Level ESD and Fault protection co-design approach on high voltage tolerant transceivers is presented. Two-stage protection network is defined for the case of ±65V CANL output stage. Methodology incorporates dual-directional SCR overshoot at triggering, calculation of parameters for the fault protection snubber clamp and internal circuit pulsed SOA limits.