FPGA-Based Implementation for QRS Detection in Electrocardiogram

This paper presents an implementation of a QRS detection algorithm in C with custom IP library blocks written in Verilog for a FPGA chip. The hardware design adds support for the processing of the data array that contains the electrocardiographic samples. Focus is put on the software and hardware structure, as well as some performance metrics – the used memory and the time for execution of the processing procedures. Final results shown that the hardware implementation is slower than the microprocessor-only implementation, its ROM usage is 700 bytes less. The RAM usage is equal in both cases. The hardware IP would also allow for other devices in the system to get more microprocessor time (e.g. interrupt handling).