A 3D FW-EM Simulation-Based PSOD Method for Characterizing On-Wafer Devices Compensating for Short Pattern Error

The commonly employed pad-short-open deembedding (PSOD) method extracts on-wafer device-under-test (DUT) characteristics by measuring the pad, short, and open patterns. However, when the previous PSOD method is applied to extract the complex DUT characteristics in high-frequency and broadband measurements, there is a problem in extraction accuracy owing to errors that occur in the short pattern. Therefore, we propose a novel PSOD method that improves accuracy by compensating for errors from short patterns using three-dimensional (3D) full-wave electromagnetic (FW-EM) simulations. In applying the proposed method to extract calculable rectangular conductors, we confirm that the extraction accuracy improved by up to 32.1% compared with that of the existing method.