An Area-Efficient Dynamic-Comparator-Reuse Noise-Shaping SAR ADC for Biosensor System

This letter proposes an area-efficient dynamic-comparator-reuse noise-shaping (NS) successive approximation register analog-to-digital converter SAR ADC for a biosensor system. An area-efficient second-order dynamic-comparator-reuse noise-shaping (DN) technology is proposed to achieve a sharp noise transfer function (NTF) with only 11.5% digital-to-analog converter (DAC) capacitance added, resulting in a good compromise between accuracy and chip area. The proposed all-in-one dynamic-comparator/dynamic-amplifier (ADD) performs the functions of dynamic comparison and dynamic amplification in different phases of the same conversion cycle, avoiding the design of two additional dynamic amplifiers and further reducing the chip area. The proposed DN SAR ADC is implemented in the 65-nm CMOS process, and the core chip area is 0.68 × 0.19 mm
²
. The measured results show that the chip consumes 0.1 μW at a supply voltage of 1 V when the sampling rate is 10 kS/s. The proposed second-order DN SAR ADC achieves a signal to noise and distortion ratio (SNDR) of 74.78 dB, a Schreier figure of merit (FoMs) of 167.8 dB, and a Walden figure of merit (FoMw) of 56 fJ/conv.-step.