Thermal-Aware Fixed-Outline 3-D IC Floorplanning: An End-to-End Learning-Based Approach

High temperature and temperature nonuniformity pose significant challenges in 3-D integrated circuits (3-D ICs). Numerous studies have explored thermal issues in 3-D IC floorplanning. However, most existing handcrafted heuristic algorithms suffer from long iteration cycles, resulting in inefficient thermal management and no guarantee of optimal performance. In addition, with the increasing complexity of modern integrated circuit design, current floorplanning techniques encounter the “curse of dimensionality” and struggle to optimize large-scale cases. To address these challenges, this article proposes a novel end-to-end learning-based approach for thermal-aware fixed-outline 3-D IC floorplanning. In the tier assignment stage, we utilize a deep
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-means clustering algorithm to allocate modules to different tiers, aiming to achieve an improved cross-tier power distribution. In the global distribution (GD) stage, we formulate the floorplanning problem as a Markov decision process (MDP). By combining graph convolutional networks (GCNs) with a multiagent deep reinforcement learning (MADRL) algorithm, we optimize the positions of modules and through-silicon vias (TSVs), while incorporating an attention mechanism in the centralized critic to enhance cooperation among agents. Finally, in the TSV assignment (TA) stage, we refine the TSV positions using the MADRL algorithm, further reducing wirelength and temperature in 3-D ICs. Experimental results demonstrate that our proposed approach outperforms state-of-the-art heuristic-based 3-D IC floorplanner in terms of wirelength and temperature optimization.