Floating Point Multipliers Based On Vedic Mathematics

Multipliers form the core of all Digital systems. There is a growing demand for low-delay multipliers in a wide range of digital signal processing applications. These applications need high-speed processing and low latency. As demand for these applications continues to grow, the need for floating-point arithmetic that is both fast and accurate has also increased. In this paper, the Vedic mathematics technique Urdhva-Tiryakbhyam (UT) sutra is used to build a Floating-Point Multiplier. The paper aims to put forth the better performance of Vedic multipliers. The Vedic Multiplier is analyzed and compared with a Conventional Multiplier- Array Multiplier as well as with a widely used Wallace tree Multiplier. The designs were created using Cadence EDA Tool's 90nm standard cell library. The comparisons and benchmarking are done by the tools provided in Virtuoso. The Vedic multiplier is implemented with different adders and compared, and a conventional multiplier is also implemented and compared with the Vedic counterpart. The power and delay are compared among the multipliers.