Implementation of LMS Algorithm Based Adaptive Filter Using Verilog HDL

This article focuses on the deployment of minimum mean square algorithm filters on Field Programmable Gate Array (FPGA). The principle and structure of the Least Mean Square (LMS) algorithm filters are briefly discussed. An improved and high-speed FPGA deployment method is proposed. The full pipelined structure of the LMS adaptive filter is implemented by adding a counter module to control the global structure of the entire algorithm. The basic modules for deploying the LMS algorithm adaptive filter, such as the counter, are given. Comprehensive simulations of the adaptive filter deployed in this way are carried out and compared with the original LMS algorithm filter. Results show that this proposed method could achieve high maximum frequency.