An 18.2μW 101.1dB DR Fully-Dynamic ΔΣ ADC with Partially-Feedback Noise-Shaping Quantizer and CLS-Embedded Two-Stage FIAs

This work proposes a low-power, high-precision fully-dynamic delta-sigma ADC for sensor applications. A partially-feedback noise-shaping SAR quantizer is employed with digital filters to achieve high SQNR and reduce the data-weighted-averaging (DWA) complexity. Furthermore, assisted by correlated-level-shifting (CLS) and dynamic-body-biasing (DBB), an 87.2dB dc gain two-stage FIA is proposed, whose stability and noise performance are also optimized. Fabricated in 55nm CMOS under a 1.2V supply, the prototype achieves 98.9dB SNDR and 101.1dB dynamic range (DR) while only consuming 18.2$\mu$W at a signal bandwidth of 1.6kHz. This corresponds to an SNDR-based Schreier FoM of 178.3dB, a DR-based Schreier FoM of 180. 5dB, and a Walden FoM of 79.0fJ/conv.