A Polymer-Based Embedded Silicon Fan-Out Packaging (P-eSiFO) Method for High-Density Chiplet Packaging

Embedded silicon fan-out packaging (eSiFO) features excellent electrical and thermal performances as well as scalability to 3-D packaging and heterogeneous integration, making it a promising packaging technology for chiplet integration. Nevertheless, conventional eSiFO implementation resorts to a dry film vacuum lamination process for surface passivation of reconstituted wafers, which is challenged by low lithographic resolution, limited compatibility, difficulty in filling high-aspect trenches, and elevated costs due to the inherent attributes of dry film materials. This work proposes a new surface passivation method of eSiFO, which uses Parylene to fill trenches and polyimide (PI) to passivate the reconstructed wafer surface. The trench with an aspect ratio greater than 10 and a width less than
$5 ~\mu \text{m}$
can be filled successfully. The height difference of the reconstructed wafer surface after polymer passivation was less than
$1 ~\mu \text{m}$
. Finally, three different wiring methods were proposed to implement two-layer high-density damascene wiring (linewidth/line space
$ < 2 /2 ~\mu \text{m}$
). This approach is characterized by its ease of implementation, cost-effectiveness, superior compatibility, high chip area efficiency, minimized die shift, and capability to facilitate high-density redistribution layer (RDL) wiring. Given these attributes, this approach indicates a propitious future for advanced packaging techniques of chiplet.