FPGA Implementation of the AES Algorithm with Lightweight LFSR-Based Approach and Optimized Key Expansion

Cryptography is essential for ensuring the confidentiality, integrity, authenticity, and non-repudiation of information in the digital age. It serves as a fundamental building block for secure systems, protecting sensitive data and enabling trusted communication and transactions. Hardware-based cryptography offers higher levels of security, performance, and compliance. The Advanced Encryption Standard cipher offers enhanced cryptographic security by effectively scrambling the plain text, providing a robust level of protection. This work introduces a novel method to achieve an efficient implementation of the Advanced Encryption Standard block cipher cryptographic algorithm on the Intel DE-10 Lite FPGA development board. The design incorporates architectural optimizations for the forward and inverse AES SubBytes transformation (S-box and inverse S-box) using Linear Feedback Shift Registers. Furthermore, algorithmic optimizations are incorporated to reduce memory storage requirements during round-wise key expansion. The proposed design handles AES encryption and decryption seamlessly, offering a complete solution for both processes. The hardware implementation of the proposed design achieved a remarkable reduction in device utilization for AES-128, decreasing from 91% to 29%.