Power efficient VLSI architecture based logistic regression for classification of breast cancer

Machine Learning applications involve arithmetic operations, mainly floating-point computations and parameters that are the source of power consumption. This paper proposes a power efficient VLSI architecture, trained and tested on Wisconsin breast cancer (WBC) (original) data set to classify benign or malignant. The precision scaling is carried out on the logistic regression model’s parameters such as weights, bias, and standardized data points, which reduces the complexity of floating-point adder architecture and further the approximate adders are replaced in the mantissa integer adder of floating-point adder architecture, leading to a reduction in area, power, and delay without much compromise in accuracy. Results show an improvement of 93.12% in area, 97.4% in power, and 74% in delay are achieved by half-precision compared to the double-precision. Similarly, there is an improvement of 73.34% in area, 84.63% in power, and 55.65% in delay for single-precision w.r.t double-precision. Further improvement in the area, power, and delay is achieved by replacing the mantissa integer adder with various approximate adders in 16-bit floating-point adder architecture. We proposed five Logistic Regression Models (LRM1 to LRM5), out of which LRM5 is best because it occupies 94.08% less area, consumes 98.21% less power, and 77.68% less delay than the exact double-precision model. Further, results show that LRM5 achieves an improvement of 14.04% in area, 29.66% in power, and 14.12% in delay compared to the half-precision model.