A 20–43-GHz Low Phase Variation VGA With Feedforward Signal Suppression and Impedance-Invariant Techniques in 65-nm CMOS

A variable gain amplifier (VGA) featuring wide bandwidth and low phase variation is presented for the new generation phased arrays supporting multiple-frequency bands simultaneously. In this article, the mechanism of phase variation in common-source (CS) CMOS amplifier cell is investigated in detail. As revealed by this analysis, the parasitic capacitor ${C} _{\text {gd}}$ and the magnetic coupling among inductors as well as parasitic capacitors in layout inducing by interconnection lines are some of the key factors that generate feedforward signal, which leads to the phase variation. The other is the inconstant input and output admittance that result in phase deviation over a wideband region. To achieve low phase variation over broadband for CMOS CS VGA, an innovative phase compensation method based on feedforward signal suppression (FSS) and impedance-invariant techniques is proposed. Specifically, the active cross-coupling neutralization topology is employed to suppress the feedforward signal generated by ${C} _{{\text { gd}}}$ . Meanwhile, an isolation enhancement layout approach aiming at mitigating the inductive coupling and parasitic capacitors in layout is proposed. Besides, a control circuit based on the impedance-invariant technique is developed to minimize the impedance variation. As a result, a low phase variation VGA with broadband phase compensation is achieved. The measured gain control range is 23 dB, with a 3-dB bandwidth of 20–43 GHz and a peak gain of 15 dB. The measured phase variation is <2° in 18–36 GHz and <6° across 18–45 GHz. The noise figure and input-referred ${P} _{\text {1 dB}}$ are 5.5 dB and −18 dBm in the maximum gain state, respectively. The measurement also shows the proposed VGA has good robustness against the variation of supply and temperature. The VGA consumes 30.8 mW from a 1.1-V voltage supply. The chip is fabricated in a standard 65-nm CMOS process and the core area is 0.34 mm2.

I. Introduction

In recent years, the phased arrays implemented in CMOS technology are increasingly popular with the demand for low cost and high integration [1], [2], [3], [4], [5]. In phased arrays, variable gain amplifier (VGA) and digital step attenuator (DSA) are implemented to provide amplitude weighting to achieve low sidelobe [6]. In order to maintain beam direction and achieve low sidelobe at the same time, VGA and DSA need to suppress the phase variation [7]. DSAs are generally implemented in the forms of distributed type [8], [9] and switched type [10], [11], [12], featuring high linearity, bidirectional operation, and power-free. However, in the millimeter-wave (mm-wave) frequency band, DSA typically has large insertion loss, which is detrimental to phased arrays. Benefiting from the low phase variation and higher gain, VGA is more attractive in mm-wave applications. Besides, VGA can be integrated with low noise amplifiers or active phase shifters [13], [14], greatly reducing the size of phased arrays.