Stress and Fatigue Life Studies of Solder Joints in an Advanced Packaging with Chiplet

Aiming at the structural reliability problem in the 3D packaging structure of Chiplet with TSV (Through Silicon Via), combined with finite element analysis, the stress, fatigue life of the solder joints, and the deformation degree of the TSV are predicted under the thermal cycle condition. The simulation results show that the equivalent stress of the upper layer is larger than that of the lower layer, and its minimum life is also lower. In addition, it is more likely to fail at the edge far from the chip center and in contact with the TSV. Compared with the lower TSV, the deformation degree of the upper TSV increases, and the deformation degree of the TSV farther away from the chip center is larger and shows a ladder distribution in the diagonal direction. Therefore, in the actual production, we should pay more attention to the position where the solder joints of the upper chip, at the edge position, contacts the TSV.