Programmable Delay Element Using Dual-Port FeFET for Post-Silicon Clock Tuning

The discovery of ferroelectricity in doped HfO2 has led to its widespread use in various applications, including embedded non-volatile memories and deep learning acceleration. The dual-port FeFET, with separate read and write terminals, has opened up new possibilities for employing tunable threshold voltage transistors in circuits. One such application is the programmable delay element (PDE) used to adjust the delay or frequency based on a control voltage. In this work, we presented a PDE design based on dual-port FeFET that uses the least number of transistors, provides non-volatile storage of the program state, and achieves a wide tuning delay range of 610 ps. Additionally, we demonstrated the application of the proposed PDE in mitigating the effects of circuit aging by selectively adjusting the clock skew of critical path flip-flops. Compared to existing guardband-based approaches, our method achieved a performance gain of approximately 10%.