A Novel Single-Ended Fault Location Algorithm for Digital Distance Relays Based on A New FPGA Design

This paper presents a technique to locate fault positions and mark protection zones for digital distance-relay designs using the field of programmable gate array (FPGA), and further discusses the performance concerning the value of fault voltage, relay-side impedance, and fault detection speed of the proposed design. Moreover, the suggested technique follows the concepts of the system-on-chip (SOC), which makes engineers easily improve and integrate the protection devices in the future.