Design and Implementation of Dual-Mode Support Vector Machine (SVM) Trainer and Classifier Chip Architecture for Human Disease Detection Applications

This paper proposes a low-latency dual-mode support vector machine (SVM) chip hardware architecture for human disease detection applications. It can simultaneously support the on-line SVM trainer and classifier both for linear and non-linear operating modes. In addition to the proposed hardware architecture, we also develop three effective design techniques, such as Queue-based Fast Selection (QFS), Dual-mode Linear and Non-linear Kernel (DLNK), and Low-latency Lagrange-multiplier-value Updater (LLU). For the ASIC implementation, our developed work with TSMC 40-nm multi-Vt CMOS technology only occupies a total core area of 0.249 mm2 in chip layout. After system validation with seven representative datasets, the operating frequency of our chip is up to 452 MHz. For linear and non-linear modes, the according power dissipates 54.2 mW and 71.4 mW, respectively. While manipulating 1024 training data for linear and non-linear modes, the worst-case training latency is only 1.8 ms and 99.0 ms, respectively. In addition, under the superior accuracy, true positive rate (TPR), and true negative rate (TNR) performance, the classification throughput for linear and non-linear modes is 2.42 GBps and 4.74 MBps, respectively.