Voltage Level Detection for Near-VTH Computing

Voltage level detectors (VLD) are used to monitor the supply voltage in integrated circuits (ICs) to determine when the system can initiate computation. The VLD must detect its own supply voltage, which is more challenging for low-voltage applications such as near-
$V_{\mathrm {TH}}$
computing (NVTC), which also requires low latency and rapid supply changes; furthermore, internal races in the VLD may cause false indications or glitches in the system and should be prevented by design. This work presents a glitch-free VLD that can detect supplies as low as 385 mV at a power of 217 nW and a measured latency of 10
$\mu \text{s}$
. This was achieved by inserting a deterministic delay into one of the internal nodes, as well as low-voltage circuitry. The circuit is fabricated in a 65 nm CMOS process and occupies a footprint of 6900
$\mu \text{m}^{2}$
with a measured temperature drift of 105
$\mu \text{W}/^{\circ }\text{C}$
and a sigma variation of 8 mV across 32 units. These characteristics make the circuit attractive for the near-threshold computing segment.