Integration of Soft Defect Localization (SDL) and Electro-Optical Probing (EOP) in Root Cause Investigation for Time Delay Related Issue

In this paper, combination of electrical fault isolation analysis of Soft-Defect Localization (SDL) technique and Electro-Optical Probing (EOP) technique for time delay issue are discussed. The integration of both techniques effectively pinpoints the Front-end-of-line (FEOL) or Back-end-of-line (BEOL) wafer process defects for time delay related issues. EOP will investigate the switching activities of the transistors and display its representative voltage level, but the effect of the delay will only be identified by analysts at the subsequent stage of logic or the fan-out driver from the failing signal node. By back tracing the circuitry with comparison to correlation unit, the EOP analysis is capable to isolate the delay at suspected signal routing but unable to determine the point of interest for physical analysis purposes. The estimated defect location can be further narrow down by using the SDL technique. The paper below describes the EOP characteristic of the transistors during time delay occurrence and the integration of SDL technique in FA flow for best physical defect region estimation.