Optimization of Physical Failure Analysis Process to Minimize Transistors Degradation from Electron Beam for Advance Technology Nodes

In this paper, authors investigated the effects of SEM Vacc during Physical Failure Analysis on transistor’s electrical parameters, specifically I-off, I-sat and Vt. It was verified that 2kV SEM Vacc is causing significant transistor degradation in advance technology nodes sample, and 1kV also causes non-negligible transistor degradation for device beyond 5nm, and thus, it is not suitable for its front-end-of-line Physical Failure Analysis. It was proposed to align all SEM steps to maximum of 0.5kV when reaching FEOL to prevent transistors parameters of the most advance technology node samples from being altered unnecessarily.