An Optimized Linear Regulator Circuit for Digital Chip

Using the method of inserting a fast-response buffer stage between the error amplifier and the power transistor, combined with a single-stage folded cascode amplifier circuit and a PMOS transistor power device, an optimized linear regulator circuit structure for digital chips is designed. Based on the 0.13um process library of SMIC, the output voltage is 1.204V, the power supply voltage regulation rate is 1mv/V, the response time is less than 1.15us, the load regulation rate is 19.8uV/V, the maximum load current is 20mA, the load capacitance is 2~100pF, and the quiescent current is 6.97uA. The simulation results show that the circuit has superior performance parameters, simple structure, easy implementation, no off-chip capacitance, fast instantaneous response, small static current. It can provide a stable low voltage power supply for digital chips, and has high application value.