Methodologies of Cascading to Realize High-Voltage Cascaded Super Cascode Power Switch

Development of high-voltage (HV) high-current (HC) power semiconductor devices is limited due to relatively low yield, expensive material and fabrication costs, and retracted dynamic performance from paralleling many HV, low-current (LC) devices. An alternative is a serial connection of low-voltage (LV) HC devices to create a supercascode power switch (SCPS). This article describes a methodology of cascading SCPSs to realize an even higher voltage cascaded supercascode power switch (CSCPS), which optimizes switching through multilayered cascades of normally-on devices, e.g., JFETs or depletion-mode GaN HEMTs. The method provides a topology optimization of cascaded cells dependent on switching losses, net charge reduction in network capacitors, and avalanche energy management. Simulation and test results are provided for a single-layer “2S-3C” 6-kV CSCPS. The 6-kV JFET CSCPS showed 408-
$\text{m}\Omega $
ON-resistance, leakage current of 0.7 mA at 4.8 kV, and 40-ns rise with 30-ns fall in current at 4 kV/20 A.