Vertical Charge Loss Induced by Defect Coupling at SiO2/Si3N4 Interface in 3D NAND Flash Memory

In order to provide an underlying mechanism for vertical charge loss in scalable 3D NAND flash memory, the defect coupling is investigated systematically based on ab initio calculations. We found that the trap energy levels of V
N
-H defects in Si
3
N
4
CT layer are close to the Vo-H defects in Si02 layers, which leads to defects coupling directly for vertical charge loss, but the Vo defect in SiO
2
seemed so far away. However, the Vo defects still cause the vertical charge loss during Program/Erase cycling, due to the defect coupling with the electric field at SiO
2
/Si3N4 interface. It is concluded that the defects coupling could result in vertical charge loss. Hence, more attention should be paid to interface defect processing for robust reliability 3D NAND Flash Memory.