An Analysis on the Effectiveness of 2 and 3 Terminal Capacitors in PDN Design

The parasitic inductance of a capacitor depends on its physical structure. Due to the geometry of 3-terminal capacitors, they boast a lower parasitic inductance compared to 2-terminal capacitors of the same and possibly smaller package sizes. While the parasitic inductance of a single 3-terminal capacitor may be lower, using multiple 2-terminal capacitors may result in similar performance. In this work, the inductance of 2-terminal (0201, nominal 2.2 uF) and 3-terminal (0402, nominal 4.3 uF) capacitors is extracted and compared through measurements. From our de-embedding method and characterized capacitors, the inductance of 2-terminal capacitors is only about ~20 pH higher than the characterized 3terminal capacitor. On a power net of a real product, 3-terminal capacitors of the same type as characterized were replaced with 2-terminal capacitors of the same type as characterized. From measurement results, the measured inductance at 100 MHz is lower by only about 3.45 pH, or 2.62%, when using 3-terminal capacitors.

I. Introduction

In the design of power distribution networks (PDNs) for printed circuit boards (PCBs), decoupling capacitors may be used to filter out noise or act as a temporary source of charge. The performance of a decoupling capacitor depends heavily on its inductive parasitics, characterized as its equivalent series inductance (ESL), and is a function of the capacitor geometry. The ‘common’ multi-layer ceramic capacitor (MLCC) is the 2-terminal capacitor, whose ESL is directly related to the package size. Via placement and routing strategies aside, smaller package capacitors translate to lower inductances when compared to larger package capacitors of the same design. To further reduce the inductance contributed by the capacitor body, many other capacitor geometries have been explored. Among them, there exist multi-terminal capacitors, such as the 3, 8 and even 10-terminal capacitors [1], which leverage both multiple and shorter internal current paths for much lower ESL, often lower than even 2-terminal capacitors of comparably smaller package size.