A Thermal-aware DC-IR Drop Analysis for 2.5D IC

With the trend of higher integration, 3D/2.5D IC solutions such as CoWoS (Chip-on-wafer-on-substrate) have become more popular in recent years. Power integrity (PI) is always a critical part of the design especially when the power consumption requirements are important specs for high-performance computing. DC-IR drop is one of the criteria within power integrity considerations. However, ordinary electrical-only simulation for DC-IR drop will be an underestimation because it neglects the copper conductivity dropping due to the temperature rising. Thus, an engineering solution for electrical-thermal co-simulation is important to help to provide both an accurate PI analysis and the proper mitigations of the IR drop along the power rails. This paper uses a 2. 5D IC chiplet as an example to conduct the thermal-aware DC-IR simulation workflow. By iterating and exchanging the power map and temperature map files between an electrical simulator and a thermal simulator, detailed layer-by-layer IR drops and the temperature map results can provide good insights for efficiently mitigating the IR drop for PI by establishing a better cooling condition in thermal solution.