Cyclic Timing Path Evaluation Using Commercial Static Timing Analysis Algorithms

Many circuit design methodologies employ combinational logic with feedback to realize logic functions. Obtaining accurate delay values for cyclic timing paths is an impediment to the adoption of these technologies. Static timing analysis (STA) algorithms are the standard for digital timing validation but require that timing arcs form directed acyclic graphs. STA algorithms can be used to evaluate cyclic timing paths with a loss in accuracy by cutting cycles into acyclic segments and summing each segment in a cyclic timing path. This paper reports on sources of error in using static timing analysis to evaluate acyclic timing segments of cyclic timing paths, and shows that using timing segments to evaluate cyclic timing paths with STA can lead to both overly pessimistic and incorrect delay calculations. A method is presented to accurately evaluate segmented cyclic timing paths and detect drafting conditions using STA tools. The algorithm is executed on a number of common cyclic circuits and has been shown to accurately evaluate segmented cyclic path delays compared to fully unrolled circuit paths for different operating conditions, fanout loads, and timing path cuts.