Design and Evaluation of M-Term Non-Homogeneous Hybrid Karatsuba Polynomial Multiplier

Finite-field multipliers progressively plays a crucial role in modern cryptography systems. While much attention has been given to the development of area-efficient Karatsuba multipliers as a means of bolstering encryption capabilities, there remains a vast and untapped realm of design space yet to be explored. An innovative technique that has emerged in this area involves the implementation of a Composite M-Term Karatsuba-like Multiplier, which integrates a schoolbook multiplier (SBM) at lower bounds to enhance performance. However, the approach of breaking down operand bit-widths homogeneously along the stages may not result in optimal hardware characteristics, and further improvement can be achieved by configuring the recursive stages to non-homogeneous ‘M’ values. This paper attempts to perform an exhaustive design-space exploration of Karatsuba-like multipliers for different bit-widths and presents a methodology for designing different possible sequences for M-Term non-homogeneous hybrid Karatsuba multiplier (MNHKA). Few MNHKA designs among several sequences achieve high performance while minimizing area requirements. This study evaluates the area, delay, and area-delay-product (ADP) characteristics of pure M-Term Karatsuba multiplier (MKA), Composite M-Term Karatsuba with SBM (CMKA), and a novel MNHKA that are configured as finite field multipliers for different popular bitwidths. In addition, this study also introduces a novel Matlab-based framework that enables the generation of an optimized hardware design code for MNHKA design with customizable sequence and operand sizes. The proposed MNHKA design was implemented and verified on ZYNQ ZCU-104 FPGA Board and also synthesized using 45 nm technology library on Cadence-Genus tool. The implemented FPGA results with LUTs utilization and delay metrics clearly indicate that the proposed category of MNHKA polynomial multiplier outperforms SOTA designs for various bit-widths. Specifically, the proposed design achieves an ADP improvement of 12.33% for a bit-width of 64, and greater gains of 21.15%, 27.74%, and 23.045% for higher order bits of 409, 1350, and 2500, respectively, when compared to CMKA(STOA) multiplier. The experimental results of ASIC flow resulted in an impressive maximum footprint saving of 47.61% as well as significant ADP gains of 45.72% for the 1350-bit design, and also achieved ADP improvement of 16.42%, 15.56%, and 22.59% for bit widths of 64, 409, and 2500, respectively, when compared to CMKA design. All the designs are made freely available for further adoption to the researchers and the designers community.