High Sensing Margin Sensing Amplifier with Improved Reliability for STT-MRAM

spin-transfer-torque magnetoresistive random access memory (STT-MRAM) is considered to be one of the leading candidates for next general memory due to its high access speed, unlimited endurance, excellent integration density, radiation hardness and outstanding compatibility with CMOS process. STT-MRAM has been extensively studied for last-level cache and energy efficient applications. Sensing operation remains reliability issue owing to the inevitable process variations, voltage and temperature fluctuations. This paper proposes a novel reliability enhanced high sensing margin sensing amplifier (HSM-SA) for STT-MRAM. Simulation is executed based on 40-nm CMOS design kit and 40-nm MTJ model taking account into temperature behaviors. Simulation results show that proposed HSM-SA achieves more than 4× sensing margin of conventional sensing circuit and the highest sensing yield compared to previous work over a wide temperature range (-55°C~125°C).