FDM: Fused Double-Multiply Design for Low-Latency and Area- and Power-Efficient Implementation

The double-multiply (DM) operation
$(x \times y \times z)$
is frequently used in computing. The traditional design based on two serial multipliers (without fusion) leads to significant area requirements and critical path delays of the circuit. In this brief, we propose a fused double-multiply (FDM) design for low-latency and area- and power-efficient implementation. In the first multiplication operation, the modified Booth (MB) encodings of the carry
$(C)$
and sum
$(S)$
are generated separately instead of being added to each other directly. After the partial products are compressed to
$C$
and
$S$
by the carry-skip adder (CSA),
$(C+S)\times z$
is calculated via the fused add–multiply (FAM) technique. Synthesized results show that the proposed hardware achieves an 11.54% reduction in the minimum delay compared with the traditional design. In addition, our design saves 17.40% area and 26.86% power compared to the traditional design when achieving the same delay.