Instruction Profiling Based Predictive Throttling for Power and Performance

Technology scaling has long been the driving force for reducing power consumption in microprocessor design. As scaling has reached its limits, new techniques are being adopted to address the power problem. Throttling is an architectural mechanism that slows down the pipeline stages to reduce instant dynamic power. However, power savings due to throttling is achieved at the expense of performance degradation. Throttling is commonly applied at fetch, issue, or commit stages where slowing down a particular stage may reduce dynamic power. A balanced bandwidth of fetch, issue, and commit are maintained in designing a pipeline such that execution can flow seamlessly. However, case studies have shown that bottleneck exists at different pipeline stages that result in performance loss. The loss of performance also indicates wasted dynamic power due to pipeline flush. In this paper, we use instruction profiling based on benchmark traces to identify instructions that are causing a significant bottleneck in the targeted processor architecture. Knowledge of the probable residence of congested instructions at different pipeline stages can enable effective CPU throttling. This paper shows that instruction profiling based predictive throttling at fetch and commit stages can save dynamic power at minimal performance loss.