Automatic Layout Symmetry Extraction for Analog Constraint Learning

Due to the sensitivity of analog circuits, symmetry constraints are used to guide analog layout synthesis. Recently, machine learning outperformed traditional methods in detecting symmetry constraints. However, its performance relies on lots of labeled data, which is labor-intensive to obtain. We propose a method to automatically extract symmetry information from legacy layouts, which generates enough labeled data, enabling a powerful graph neural network to fully exploit its capabilities. The experiments demonstrate the proposed method can correctly and quickly extract symmetry constraints from layouts. Mean-while, our supervised model outperforms both the most current supervised and unsupervised models on symmetry constraint learning.