A Multi-Dimensional Weight Partition Algorithm for FPGA Prototype Simulation

As the complexity of circuit design increases, single FPGA can no longer meet the requirements of logic simulation and rapid prototyping, so the circuit design needs to be partitioned into multiple parts, and then it can use multiple FPGA systems for simulation. When RTL-level code is modeled as an undirected graph, the weight of vertex is multidimensional and the edge is weighted. In order to meet the demand of multi-FPGA platform, we modeled the RTL-level code into an undirected graph, whose vertex weight is multidimensional, corresponding to different resources of FPGA platform, and the edge is weighted.A new partitioning algorithm should satisfy the following two requirements. Firstly, the multi-dimensional weight of each partition is below the FPGA threshold in each dimension. Secondly, the partition algorithm should minimize max_cut, where max_cut is the largest cut size between all partitions. In this paper, we propose a partition algorithm that meets the above requirements.