Multiple-Input Switching Modeling with Graph Neural Network

Multiple Input Switching (MIS) poses great challenge in Static Timing Analysis (STA) with unexpected setup or hold violations due to temporal proximity among transitions at different inputs of gate. Most prior empirical and learning based models are ad hoc techniques which should be applied to each gate separately and ignore the relation of MIS with transistor-level gate topology, leading to poor estimation accuracy and/or considerable characterization effort. In this work, a Graph Neural Network (GNN) based model is proposed to predict MIS-SIS Difference (MSD), which is trained jointly as a unified model by mapping transistor-level gate topology into nodes and edges of graph. The proposed model was validated under TSMC 16nm process for a set of multiple-input gates and paths from ISCAS‘85 and TAU benchmarks. Experimental results demonstrate excellent agreement with golden SPICE simulation results by this work with NRMSE error less than 0.73% in average for all validated gates. Comparing with prior learning based approach, our model achieves 2.7× characterization effort reduction with comparative accuracy. The predicted path delays with MIS effect with our model is highly consistent to SPICE simulation results with the average error 2.0%.