Topology Generic DC-Model for Accelerating Analog Circuit Optimization

For speeding up analog transistor sizing, in recent decades, much research efforts have been devoted to pursuing more efficient optimization algorithms. However, expensive SPICE simulation has been one of the most important factors that lead to high time costs. In this paper, we focus on handling the challenge of automatic sizing for OTA (Operational Transconductance Amplifiers). Through modeling analog circuits, a topology generic DC-Model is proposed to predict the performances of different circuits in our OTA library. OTA performances that were previously obtained from multiple testbenches can now be directly predicted by our model via one DC analysis. We leverage graph neural networks and attention readout operations in our model to deal with different input structures and improve prediction precision. We show that our model can achieve relatively accurate predictions for all OTAs in the library. Different from the previous work that focused on optimization algorithms, this work provides a new idea for analog reuse from the perspective of circuit simulation.