Total Ionizing Dose Hardening of Planar SOI MOSFET Through an Optimal Design Combining Embedded Void and H-Gate Structures

A novel device structure is proposed for total ionizing dose (TID) hardening, which combines H-gated MOSFETs with void-embedded silicon on insulator (VESOI) substrate. At total doses up to 3Mrad(Si), the shift of threshold voltage (
$\Delta {V}_{\text {th}}{)}$
is only about 60mV/dec and non-discernable changes in off-state current (
${I}_{\text {off}}{)}$
were observed. Furthermore, TCAD simulation results indicate that nearly all leakage paths caused by radiation-induced trap charges are effectively eliminated in our H-gated VESOI MOSFETs. This device structure also exhibits high tolerance for variation in void height under different fabrication conditions. The exceptional radiation immunity and compatibility with planar CMOS processes make it a competitive option for anti-irradiation applications.