Simulation study on the characteristics of planar gate VDMOS power devices

VDMOS is a semiconductor power device widely used in electronic circuits, with the advantages of fast switching speed, high input impedance, high operating frequency, and good thermal stability. In this paper, a planar gate VDMOS simulation model is established based on numerical simulation software, and its reverse breakdown characteristics, output characteristics, and transfer characteristics are simulated and analyzed. The research results show that the thickness and doping concentration of the drift region, the width of the JFET region, and the junction depth and doping concentration of the P-body region all have certain effects on the breakdown voltage and specific on-resistance of the device. If the breakdown voltage of the device is higher, the low-doped N-type drift region is required to be thicker. But at the same time the current path is longer, and the specific on-resistance will increase accordingly, increasing the on-voltage drop and on-state loss of the device. Within a reasonable threshold voltage range, a compromise design has been made between the breakdown voltage and specific on-resistance of the device By optimizing the parameters of the drift region, JFET region, and P-body region, a VDMOS with a withstand voltage of 650 V and a specific on-resistance of 0.477 mΩ·cm
²
is finally obtained.