A 12Bits segment SAR ADC with low power switching method

Aiming at the successive approximation register (SAR) analog to digital converter (ADC) with low power application requirements, the SAR ADC module has been optimized. A V
CM-based
switching method is used to design a segment capacitor array with upper plate sampling method to decrease the power consumption of the capacitor array module during conversion. On the other hand, connect the output of the two-stage dynamic comparator to the digital logic gate to construct asynchronous logic, and provide feedback to generate the clock signal of the comparator, avoiding the external high frequency clock, reducing the power consumption and improving speed. Based on the SMIC 28 nm CMOS technology, the ADC was simulated and verified on Cadence platform. The ADC achieves ENOB of 11.98 bits and SFDR of 90.90 dBc, and whole ADC consumes 49.79 μW under a 0.9 V supply voltage at a sampling rate of 20 MS/s with a Figure of merit (FoM) of 6.98 fJ/conv-step.