Three-level DC-DC Buck Converter Architecture Using Digital Pulse Width Modulation

This study demonstrates a high efficiency 3-level DC-DC buck converter using DPWM (digital pulse width modulation). It is mainly featured with the replacement of traditional flying capacitor with a capacitive voltage divider, which will constantly maintain the half of the supply input voltage. Consequently, one of the power MOSFETs in the output stage will be removed to reduce conversion loss. The duty cycle is found to be as high as 93.75
^%
and the peak efficiency is 98% at 6.25 MHz switching clock rate by all-PVT-corner simulation.