A Dual-Cryptographic Coprocessor for Authenticating WBAN Applications

Wireless body area networks (WBANs) transmit highly sensitive human physiological data, which requires robust security measures to prevent data leakage. However, due to the small size and low power consumption limitations of WBAN devices, the hardware computational resources and speed may not meet the traditional cryptographic computation requirements. Therefore, the need for low-power data encryption circuits is becoming increasingly urgent. This paper proposes a dual-cryptographic coprocessor that accelerates both RSA and advanced encryption standard (AES) cryptographic algorithms for authentication and data encryption in WBAN applications. The coprocessor is integrated with a RISC-V processor to construct a programmable WBAN system for supporting authentication and data transmission between smart WBAN chips. The proposed design was implemented in a 55nm CMOS technology. The overall WBAN system operates at a clock frequency of 100 MHz with a power consumption of approximately 11 mW, fulfilling the authentication and data encryption requirements.