Acceleration of 2D SAR Imaging on FPGA by Reducing off-chip Memory Accesses

Terahertz (THz) Synthetic Aperture Radar (SAR) is a powerful and emerging imaging technique that is capable of providing high-resolution images in the sub-millimeter range. One of the primary applications is the environment mapping and profiling with unmanned aerial vehicle (UAV) based THz SAR. Field-Programmable Gate Arrays (FPGAs) have demonstrated promising results in accelerating signal processing applications. FPGAs are able to meet the real-time requirements for environment mapping and also have the advantage of low power consumption. In this paper, a memory-optimized embedded platform is proposed for 2D SAR imaging. Since off-chip memory access latency and energy consumption are dominant in 2D SAR, this work aims to reduce off-chip memory accesses and manage on-chip memory usage to accelerate 2D SAR. The proposed 2D SAR is implemented and evaluated on a Xilinx Zynq MPSoC FPGA board. The experimental results show 86.2$\times $ improvement in term of execution time compared to the MATLAB model running on a single CPU (intel 7-4790 @3.7 GHz).