Architectural Design of Built in Self-Test for VLSI Circuits using LFSR

The term “built in self-test” (BIST) refers to a method of circuit design that facilitates self-testing. The circuit is put through its paces by generating test patterns in this system. Circuit Under Test (CUT) refers to the intended target of the testing. BIST is employed because manual testing makes the testing phase more important than any other step during device or IC fabrication, taking up the most time and being economically unfeasible. The emphasis of this study is on the planning and execution of BIST for the verification of a combinational logic circuit. The proposed hardware includes a signature analyzer, a comparator, a signature generator, and a linear feedback shift register. The CUT is activated on the negative rising edge of the clock signal, and LFSR is a pattern generator that produces 2
^(n–1)
possible test patterns. At the rising edge of clock, the CUT’s output is fed into the signature analyzer. The signature analyzer’s output is placed through a comparison with the ideal signature value provided by the comparator. If the comparator’s output is logic ‘1’, then there is no error in CUT; otherwise, CUT has an error. The signature analyzer produces two separate signature values. The test performance obtained with the implementation of proposed BIST architecture is sufficient to overcome the drawback of the hardware complexity caused by the additional BIST circuitry. Relative to that of an externally applied test, the technique permits the use of inexpensive testing equipment throughout all phases of production. The proposed technique is developed using Hardware description language and is implemented and tested on various FPGA devices.