Design and implementation of a low-area reconfigurable and synthesizable digital loop filter for ADPLL

This paper presents design and implementation of a low area and efficient Digital Loop Filter (DLF) for ADPLL application. DLF is one of the basic building blocks of an ADPLL and used to remove high frequency contents from TDC (Time to Digital Converter) output. Digital loop filter is one of the most area consuming block in ADPLL and care is required in its efficient implementation. In Analog PLL $2^{nd}$ or $3^{rd}$ order loop filter can be implemented using R and C passive components. The absence of passive components makes ADPLL a superior choice for low area design. In ADPLL same order filter can be implemented in z-domain. This work discusses the design and implementation of a digital filter whose coefficients can be changed adaptively hence minimizing the area due to re-using of the resources (MAC units). The coefficients are made adaptive which can be controlled using an external interface as well as a number of options (for coefficients) inside the digital block. This makes the filter convenient to use and DCO can be operated with specific region of operation. Also the filter is designed and verified in HDL using standard library cells thus making it synthesizable and can be used by any CMOS technology node. In this work the filter is implemented and simulated for 65nm technology with the area of.01mm$^{2}$.