Spin Transfer Torque Magnetic Random Access Memory With Built-in-Self-Trimming After-Test Writing Strategy

A built-in-self-trimming after test (BIST-AT) write strategy for spin-transfer torque magnetic random access memory (STT-MRAM) is proposed in this work, which aims to reduce the power consumption of write operations. The voltage applied to each column of memory array during write operations is optimized. First, a multistage level shifter (MS-LS) circuit is proposed in this work. This MS-LS circuit provides step-wise output voltages which are determined by its control signal. Second, the MS-LS circuit is introduced to the BIST-AT trimming system. This trimming system consists of two main parts, and they are MS-LS block and BIST-AT block. Thus, the proposed BIST-AT writing strategy is accomplished. As the optimization results, energy consumption for write operation can be reduced by 25.1% with a slight cost of area efficiency. Consequently, the energy efficiency is improved while reaching the target yield.