Area-Aware Optimization of MRAM Crossbar Array Bit-Cell for In-Memory Computing

Recently, the crossbar array chip based on spin-transfer-torque magnetoresistive random access memory (STT-MRAM) has been proposed for in-memory computing (IMC), which enables efficient analog multiply-accumulate (MAC) operation to reduce the power consumption of artificial neural networks (ANNs). We propose three optimized designs for the 3-transistor and 2-magnetic-tunnel-junction (3T2J) bit-cell employed in the STT-MRAM crossbar array chip in terms of layout and circuit design. First, by adjusting the transistor order of the 3T2J structure, the layout area is reduced by 10%. Second, a 2-finger configuration is adopted for the access transistor to improve the write performance by 19.1%, while the layout area remains unchanged. Third, a novel 4T2J bit-cell design is proposed, in which the write performance is more balanced than that of the 3T2J one, and the bit-cell area is reduced by 20% with the concise routing.