A Time and Cost-Efficient Design Methodology to Estimate Effective Thermal Conductivities in System-on-Chips with Composite Materials

As complexity in System-on-Chip (SoC) design increases, prediction of thermal behavior in SoCs becomes much more difficult than ever, especially for stacked SoCs, such as 2.5D/3D integrated circuits (ICs). In this study, we have developed a 10-by-10 pixelated nodal network system that allows users to create as many combinations of metal patterns as possible with a minimal time consumption. More than 10,000 metal pattern cases can be generated within 5 minutes with a pattern generator using the random-walk model. Once a metal pattern is generated, a simple matrix multiplication is needed to calculate temperature of 121 nodes per a case within 0.4 second. Some of the calculation results are chosen for comparison purpose with conventional FEA simulation results and both methods show great agreement with each other, having less than 1% discrepancy. Parametric study has been conducted to understand the effect of structural parameters such as metal volume fraction, inlet and outlet width, inlet to outlet width ratio, relative distance between inlet and outlet, and pixel size on effective thermal conductivity (or ETC) of the pixelated system. Lastly, we propose a general trend line of ETC as a function of temperature gradient across the pixelated system normalized by heat conduction path length. We expect substantial savings in computational burdens to predict thermal behavior of early SoC designs without sacrificing accuracy.