Design of Negative Capacitance based Dopantfree Junctionless Nanowire Tunnel FET for Analog and Linearity Analysis

In this work, the impact of negative capacitance upon Charge plasma Junctionless Nanowire Tunnel Field Effect Transistor (NC JL NWTFET) is proposed and investigated. A dopant free technique charge plasma is applied to the proposed device which excludes the need for doping for the creation of source and drain terminals which reduces the Random Dopant Fluctuations (RDFs) and Expensive Thermal Budget (ETB). The channel length of 20nm and radius of 7.5nm is used for designing the proposed device. Simulations using Silvaco TCAD coupled with Landau Khalatnikov (LK) coefficients of ferroelectric are used. The negative capacitance approach enhances the non-hysteric operation which can ultimately be used for minimal power purposes. To analyze the ideal required bias, LK equations are used for determining the ferroelectric thickness and to calculate the impact of NC, the ferroelectric PZT having perovskite properties is used near gate as an insulator. The thickness of ferroelectric is the major factor as it can lead to hysteresis So, the thickness needs to be carefully selected. The investigation is done with the comparison of with NC and without NC upon JL NWTFET. With the negative capacitance approach the proposed device exhibited I
ON
of 1.17 (μA) at reduced operating voltage of 0.5V. Device comparison with respect to analog and linearity analysis is demonstrated proving the device capability for low power applications.