A Speed-Enhancement Technique Based on Single-Node-Detection and Bulk-Driven for Inverter-Based Amplifier in Switched-Capacitor Integrator

This brief presents a speed-enhancement (SE) technique for inverter-based amplifier (IA) in switched-capacitor (SC) integrator. Single-node detection is adopted to avoid the offset problem of conventional differential-nodes detection and makes the SE technique feasible for single-ended IA. Despite the lack of tail current source in IA, the SE technique based on bulk-driven boosts slew-rate (SR) and gain-bandwidth-product (GBW) simultaneously, achieving
$3.6\times $
faster settling. Moreover, the relationship between overshoot/undershoot of IA and GBW of SE circuit is theoretically analyzed. Large-signal analysis of SE circuit figures out the way to improve the robustness of SE technique by trimming. A SC integrator based on IA with SE technique is designed in 180-nm CMOS technology. IA with SE technique in the integrator achieves 60 dB gain and
$16~\mu \text{W}$
power consumption at 5.12 MHz of
$f_{\mathrm{ s}}$
, leading to a power-saving of 61% compared with conventional IA.